Qwenputer embeds a RISC-V CPU inside an LLM’s weights

AI engineer Divyansh Agrawal has released Qwenputer, an experimental modification of Qwen3.5-4B with a 32-bit RISC-V CPU compiled into 11 added transformer layers. The CPU uses the model’s Gated DeltaNet state as addressable RAM and can execute C and MicroPython during forward passes without an external tool executor. The repository reports that it passes the official riscv-tests suites and supports exact arithmetic, while a separate experimental filesystem checkpoint provides `put`, `append`, `get`, `list` and `delete` operations. That filesystem model supports up to 512 files and can preserve data when its relevant state is saved and restored. The project’s code is MIT-licensed, while the modified model weights are released under Apache-2.0; the main checkpoint is roughly 18.8GB and is intended for a GPU with about 24GB of memory.

Why it matters

Qwenputer tests whether a language model can incorporate exact computation and stateful storage into its own forward pass rather than calling conventional software tools. It also provides a concrete research artifact for studying how model states can implement CPU, memory and filesystem-like functions, although the approach remains experimental and computationally expensive.

Key points

  • Qwenputer combines Qwen3.5-4B with a compiler-generated 32-bit RISC-V CPU inserted into 11 additional transformer layers.
  • The CPU’s weights are computed rather than learned, and the model’s Gated DeltaNet state serves as addressable RAM.
  • The author reports passing the official riscv-tests suites and replaying about 230,000 computer-output positions with no mismatches.
  • A separate experimental filesystem model supports up to 512 files, about 53,000 tokens of text, and state save-and-restore across sessions.
  • The main checkpoint is about 18.8GB; the repository says an L4 can run it with roughly 24GB of GPU memory, though execution is slow.

Based on reporting by The original announcement and Tom's Hardware.